1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices. More particularly, it relates to a method of fabricating planar semiconductor transistors which eliminates critical alignment in registration steps which usually precede the deposition of emitter and other impurity regions.
2. Description of the Prior Art
One problem which has prevented semiconductor designers from increasing the number of transistors which can be fabricated within a semiconductor chip is the registration of one impurity region with another. As photo-and electron beam-lithographic techniques have improved in recent years, the geometries of the active regions within the chip could be decreased substantially from the present ground rules. However, the aforementioned mask registration problems have prevented this from reaching its fullest extent.
The present, widely used techniques of registration usually include the use of fiducial marks on each mask and the underlying semiconductor substrate. These marks are manually registered by a skilled operator; however, the smaller the size of the device, the greater the possibility of registration error by the operator. In addition, this technique is more costly than one which would provide for self-alignment during the fabrication process because each mask must be registered.
Relatively recently, semiconductor designers have turned to the use of said self-alignment masking techniques with blocking masks as a way of avoiding the need for perfect mask alignments at each step. U.S. Pat. Nos. 3,928,082, 3,948,694, 3,967,981 and 3,900,352, the last-mentioned being assigned to the same assignee as the present application, are examples of such self-aligned techniques. However, the manufacturing application of these processes is somewhat limited, either by the necessity for the ion implantation of one or more impurity regions through a mask or because they are useful only in forming spaced-apart regions.
In particular, it has not been possible to form accurately one impurity region within another by means of a blocking mask because of the likelihood of contact between the peripheries of the regions. In practice, this problem has been avoided by designing the masks to allow for substantial misalignment, thereby wasting space. Another solution is the well-known "butting" technique whereby the emitter and base region, for example, abut an isolation region. However, the devices fabricated in this way are not reliable.
A problem apparently not fully appreciated by designers using prior art techniques is the well known lateral undercutting of one masking layer which is disposed beneath another during an etching process. The undercut portion increases the effective masking window for impurities and could result in the overlapping of regions which should be spaced apart.